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Technical description
Full equipment name: STS ICP Multiplex Advanced Oxide Etch (AOE) system
General purpose: Deep Reactive Ion Etching of silicon oxide and silicon
Technical data:
• Reactive ion etching process with inductively coupled plasma
• Single wafer machine with carousel (2 wafers) loadlock for 100 and 200 mm wafers
• Installed gases: CH4, C3F8, C4F8, SF6, CHF3, Ar, O2
• Process pressure range: 4-95 mTorr
• Plasma power max, coil: 13.56 MHz, 3 kW, platen: 13.56 MHz, 1 kW
• Gases: CF4, C4F8, CHF3, SF6, H2, He, O2, N2, Ar
• Achived uniformity (oxide): +/- 3 % within 100 mm Si wafer
• Configured for 100 mm wafers, glue smaller pieces on 100 mm Si wafers

Tool name:
ALOES Advanced Oxide Etcher
Dry etching
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OXIDE ETCHING with recipe:  _SiO2

Etch Rate (thermal oxide) ~ 318 nm/min
Within Wafer Variability <4%
Selectivity over PR: >3.4:1 (92 nm/min for 700-1.2 PR, hard bake 1 min @ 110 degC)
Selectivity over Si: >9.5:1 (33 nm/min for <100> p-type Si)

SILICON ETCHING with recipe:  _Si

Etch Rate (<100> p-type Si) ~ 675 nm/min
Within Wafer Variability <5%
Selectivity over PR: >3.4:1 (189 nm/min for 700-1.2 PR, hard bake 1 min @ 110 degC)
Selectivity over SiO2: >3.6:1 (218 nm/min for wet thermal oxide)


Background information

Oxide Etching

  • To etch silicon oxide C4F8 is injected into the ICP and ionized which creates a mixture of fluorine and carbon heavy ions. These ions are accelerated towards the SiO2 substrate where fluorine combines with the silicon to SiF4 and carbon reacts with oxygen to CO2. The volatile etch products are removed with the continuous gas flow. For this etch, there is no dedicated passivation gas being injected. However, this does not imply that sidewall passivation is not occurring.

  • -CF2- and -C2F4- species in the plasma generate a teflon-like polymer film on the wafer surface which is continuously removed by ion milling on the horizontal surfaces. Vertical surfaces remain protected by the polymer layer.

    The radicals generated due to the polymer decomposition on the horizontal surfaces produce the chemical etching, resulting in a highly anisotropic and smooth etching profile.

    H2 is added to the gas mixture to reduce the concentration of unbound fluorine radicals by HF formation. A reduced fluorine concentration decreases its recombination with CF3+ radicals and a discharge rich in unsaturated fluorocarbons, such as CF2, is produced. As mentioned before, these unsaturated fluorocarbons are the precursors of the passivating polymers. This fluorine deficient discharge is important since it enables selective etching of Si02 over Si.

    Inert He is used to dilute the gas mixture and provides 200sccm of continuous gas flow inside the chamber. This correlates to a process pressure of 4mTorr.

Silicon Pseudo Bosch Etching

  • This etch is a mixed-mode passivated etch which provides slower etch rates and smoother etch profiles in comparison to the alternating Bosch process. It is favourable for nanoscale etching (below 2-3 um).
  • The process chemistry for etching and passivation are independent from each other which allows easy control of the etch profile. Ionized SF6 provides fluorine ions and radicals to react with silicon. The volatile etch product (SiF4) is removed with the process gases. The constituents of C4F8 plasma create polymer chains of -CF2- which are deposited on the substrate surface. This polymer layer protects the silicon from chemical etching. Acceleration of SFx and Fy ions in the electric field of the DC bias removes the passivation layer on horizontal surfaces by ion milling. Overall, this process results in passivation of sidewalls by a polymer coating whereas horizontal surfaces are etched. Unlike the Bosch process, the simultaneous passivation and etching prevents scallops in the etch profile


  • Rossnagel, Stephen M., Jerome J. Cuomo, and William Dickson Westwood, eds. Handbook of plasma processing technology: fundamentals, etching, deposition, and surface interactions. William Andrew, 1990.
  • Henry, Michael David. ICP etching of silicon for micro and nanoscale devices. California Institute of Technology, 2010.


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